Sar-Adc

Details

Veröffentlichungs-Nr.

EP4804409

Anmeldetag

6. März 2025

Veröffentlichung

9. September 2026

Rechtsraum

EP

IPC

H03M1/46

Abstract

A successive-approximation-register analog-to-digital converter (SAR-ADC), comprising at least wherein the control logic is configured to access an N-bit register in N consecutive clock cycles to apply a successive-approximation-register algorithm based on a signal provided by the output of the comparator, and the application of the successive-approximation-register algorithm comprises, in each of the N consecutive clock cycles, that the control logic sets two bits which are next to each other by using two N-control-bits as follows: - using the first N-control-bits, starting with the most-significant-bit which is initially set to a pre-defined value and proceeding to the least-significant-bit with each following clock cycle, leaves the set bit at the pre-defined value or flips the bit in dependence on the result of the comparator, and in the same clock cycle - using the second N-control-bits, starting with the bit next to the most-significant-bit and proceeding to the least-significant-bit with each following clock-cycle, sets the bit next to the most-significant-bit to the pre-defined value.

Anmelder

Firma

Photeon Technologies GmbH

Land

🇦🇹 Österreich

Fachgebiete