Systeme und Verfahren zur Implementierung von Pseudowiderständen mit Programmierbarem Widerstand und Gesteuertem Leck

Details

Veröffentlichungs-Nr.

EP4808304

Anmeldetag

2. März 2026

Veröffentlichung

16. September 2026

Rechtsraum

EP

IPC

H10D1/40, H03K17/14

Abstract

The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes a resistor unit comprising a first transistor and a second transistor. The first transistor includes a first terminal and the second transistor includes a second terminal. The first terminal is coupled to the second terminal. The resistor unit is configured to provide a first resistance between the first terminal and the second terminal. The apparatus further includes a reset unit coupled to the resistor unit and configured to provide a second resistance between the first terminal and the second terminal in response to a control signal. The second resistance is lower than the first resistance. The subject technology provides a reset mechanism that enables fast recovery from high-resistance states, ensuring precise resistance control and improved performance in high-impedance applications.

Anmelder

Firma

Avago Technologies International Sales Pte. Limited

Land

🇸🇬 Singapur

Fachgebiete