Decodierer, Decodierungsverfahren, Speichersysteme und Betriebsverfahren und Steuergeräte dafür

Details

Veröffentlichungs-Nr.

EP4811135

Anmeldetag

14. Februar 2025

Veröffentlichung

23. September 2026

Rechtsraum

EP

IPC

G06F11/10

Abstract

In an example, a decoder comprises a first processing circuit configured to: obtain a check expression and a check expression weight based on a codeword to be decoded in a current iteration and a check matrix; a second processing circuit configured to: obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration; a processor configured to: determine a flipping threshold in the current iteration based on a changing state of the check expression weight; and a bit flipping circuit configured to: output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the processor

Anmelder

Firma

Yangtze Memory Technologies Co., Ltd.

Land

🇨🇳 China

Fachgebiete