Zeilendekodierschaltung, Entsprechende Speichersteuerungsvorrichtung und Betriebsverfahren

Details

Veröffentlichungs-Nr.

EP4811360

Anmeldetag

27. Februar 2026

Veröffentlichung

23. September 2026

Rechtsraum

EP

IPC

G11C8/08, G11C16/08

Abstract

In a row decoder (10'), an input node receives a row selection signal (ln_lv) and an output node (11) is coupled to a word line (WL) of a memory. A pull-down circuit (12a) is coupled between the output node and ground and selectively couples the output node to ground when the row selection signal is asserted. A pull-up circuit (14) is coupled between the output node and a supply node (15) that provides a selectable supply voltage (shifted_supply), and selectively couples the output node to the supply node when a deselection signal (Vcomm) is de-asserted. An inverter (16) is supplied between the supply node and a shifted ground node that provides a selectable ground voltage (shifted_gnd), receives as input a control signal (V₁) from a control node (18), and produces the deselection signal. A current generator (19) sources a biasing current (I₁) to the control node. A further pull-down circuit (12b') is coupled between the control node and ground, and selectively couples the control node to ground when the row selection signal is asserted. The further pull-down circuit (12b') includes: a selection transistor (12xb) arranged between an intermediate node (302) and ground and controlled by the row selection signal; a first cascode n-channel transistor (121b') and a second cascode n-channel transistor (122b') arranged in series between the control node and the intermediate node; and a third cascode n-channel transistor (121b"), a cascode p-channel transistor (304), and a fourth cascode n-channel transistor (122b") arranged in series between the control node and the intermediate node.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete