Asynchrone Digitale Steuerschaltung, Rfid-Vorrichtung und Verfahren dafür
Anmelder: NXP B.V. 🇳🇱
Details
- Veröffentlichungs-Nr.
- EP4811664
- Anmeldetag
- 18. März 2025
- Veröffentlichung
- 23. September 2026
- Rechtsraum
- EP
- IPC
- H03K19/096, G06F9/448
Abstract
An asynchronous digital control circuit (200) includes a FSM state vector circuit (210) and a plurality of sequential logic circuits (300). A number of sequential logic circuits comprise: a first input (310) arranged to receive a sequential logic circuit analog event enable signal from the state vector circuit; a register (360) captures an occurrence of an analog event; a logic gate (370) gates an output of the register with a previous digital control circuit action (372) to provide mutually exclusive actions. A second analog input receives a respective captured analog event signal (320); and an analog event condition circuit (350) combines a plurality of analog input signals to form an analog event signal. An output is at least one action to control an analog circuit in response to the respective captured analog event signal and the sequential logic circuit analog event enable signal.
Anmelder
- Firma
- NXP B.V.
- Land
- 🇳🇱 Niederlande
Niederländischer Halbleiterhersteller mit Sitz in Eindhoven. Entwickelt Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation, Sicherheit sowie industrielle Anwendungen.
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