Mehrere Ddr-Subsysteme mit Einzelsträndefront unter Verwendung von Geketteten Phys

Details

Veröffentlichungs-Nr.

EP4814959

Anmeldetag

24. März 2026

Veröffentlichung

30. September 2026

Rechtsraum

EP

Abstract

A memory subsystem in a compute device includes a number of memory controllers in combination with one or more physical layers (PHY). A processor of the device adjacent to the memory controllers communicates processing commands for memory requests with the MCs that manages the reading and writing of data from memory via the PHY. The width of the PHY defines the amount of space required by the memory subsystem along an edge of the processor. A number PHY are accommodated within the space of one PHY beachfront through stacking PHY with respect to the memory controllers. Tunnels are provided across the PHY passing between I/O pads of the PHY that connect distant PHY to the memory controllers. The compute device can utilize larger amounts of memory supporting multiple PHY in the space of one memory subsystem.

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Firma

Google LLC

Land

🇺🇸 USA