Systeme und Verfahren zur Eingangsleckreduktion und Linearitätsverbesserung in Signalverarbeitungssystemen

Details

Veröffentlichungs-Nr.

EP4815299

Anmeldetag

3. März 2026

Veröffentlichung

30. September 2026

Rechtsraum

EP

IPC

H03F1/52, H03F3/45, H10D89/60

Abstract

The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes an input terminal configured to receive an input signal. The apparatus further includes a first circuit coupled to the input terminal, the first circuit comprising a first transistor coupled to the input terminal and a level-shifter coupled to the first transistor. A second circuit is coupled to the first circuit, the second circuit comprising a second transistor, the second transistor including a base terminal coupled to a first supply voltage. The apparatus further includes an amplifier comprising a first input and an output, the amplifier being configured to generate an output signal by amplifying the input signal. By optimizing electrostatic discharge (ESD) protection, electrical overstress (EOS) protection, and leakage control in the analog front-end (AFE), the apparatus reduces leakage current and minimizes nonlinearity. There are other embodiments as well.

Anmelder

Firma

Avago Technologies International Sales Pte. Limited

Land

🇸🇬 Singapur

Fachgebiete