Gate-Treiberschaltung, Schaltungsanordnung, Verfahren

Details

Veröffentlichungs-Nr.

EP4815306

Anmeldetag

24. März 2025

Veröffentlichung

30. September 2026

Rechtsraum

EP

Abstract

A gate drive circuit for driving at least a first and a second power transistor between switching states, wherein the first and second power transistor are arranged in parallel between a first load node and a second load node, the gate drive circuit comprising: a control signal input node configured to receive a common control signal, temperature input nodes to receive a temperature signals indicative of a temperature of the power transistors, a delay determination unit configured to determine a delay signal comprising at least one of a turn-on delay value and a turn-off delay value based on a comparison of the temperatures of the first and second power transistors, a drive signal generation unit configured to generate a respective drive signals for driving the first and second power transistors based on the common control signal and the delay signal such that a time difference between a turn-on timing of the drive signals corresponds to the turn-on delay value and/or such that a time difference between a turn-off timing of the drive signals corresponds to the turn-off delay value, a first driver stage configured to provide the first drive signal at a first driving node and a second driver stage configured to provide the second drive signal at a second driving node.

Anmelder

Firmen

Infineon Technologies Austria AG
Politecnico Di Torino

Land

🇦🇹 Österreich