EM Microelectronic-Marin

In one aspect the present invention concerns a coherent BPSK demodulator (10) for demodulating an input signal, the demodulator (10) comprising: - an analog signal input (20) to provide an oscillating modulated input signal, - a phase locked loop (12) comprising a phase detector (22), a loop filter (23), a voltage-controlled oscillator (24) and a frequency divider (25), which are connected in series, wherein in a first startup phase of the demodulator (10) the loop filter (23) is configured to become pre-charged in accordance with trimming values obtainable from a digital memory (37), - a frequency estimator (34), which during a second startup phase of the demodulator (10) is operable to determine a frequency offset between a frequency of the input signal and a startup frequency of the voltage controlled oscillator (24), wherein the startup frequency is defined by the trimming values, and which is further operable to adjust the trimming values and the startup frequency to reduce the frequency offset.

The invention relates to a method for obtaining reliable startup of a bandgap reference circuit, the bandgap reference circuit comprising a bandgap core with at least two branches, a feedback loop, and a startup circuit. The method comprises generating a startup stimulus with an initial magnitude sufficient to transition the circuit from an inactive state to an active state, controlling the decline of the startup stimulus by regulating its reduction progressively over time, and modifying local time constants of the bandgap reference circuit to prevent a condition in which the transient decline of a voltage across a first branch is faster than the transient decline of a voltage across a second branch. By doing so, the voltages across the branches of the bandgap core converge to a target operating point, ensuring a reliable startup of the bandgap reference circuit.

The present disclosure relates to an optical tracking device and a method of operation thereof, comprising emitting light towards a surface by a light source at regular first intervals of a first frequency with a first predetermined duration; receiving light reflected from the surface by an image sensor; determining image arrays from the light received by the image sensor at the regular first intervals, the image arrays comprising a first plurality of pixels; generating a first comparison array between the first image arrays generated at subsequent first intervals; determining a first displacement amount based on the first comparison array; wherein, if the first displacement amount is bigger than a displacement amount threshold, the method further comprises: emitting light towards the surface at regular second intervals of a second frequency with a second predetermined duration, determining second image arrays from the light received by the image sensor at the regular second intervals, the second image arrays comprising a plurality of pixels, generating a second comparison array between the second image arrays generated at subsequent second intervals, determining a second displacement amount based on the second comparison array.

The present disclosure relates to a system and a method for generating a compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, comprising temperature compensation data for the amplification of RF induced voltages.

The present disclosure relates to a system and a method for generating a temperature compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, comprising temperature compensation data for the amplification of RF induced voltages.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

An aspect of the invention describes a data reading system comprising two clock sources (CS1 and CS2), a configuration/access interface (C/A-I), and various logic and register modules. The system includes a configuration/access logic module (C/A-L) that receives signals from CS1 and interfaces with the data logic module (DL). The data register module (DR) stores data and provides it to a data output register module (DOR), which generates a data output signal. The system features a read window generator (RWG) and a read manager (RM) to manage reading operations. The system operates in an idle or reading state, controlling data flow based on the state of the configuration/access interface.

In one aspect the present invention concerns a rectifier circuit (10) for a passive RFID circuit (1), the rectifier circuit (10) comprising:- at least a first rectifier stage (11) comprising a first stage input (14) connectable to a first antenna port (6) and comprising a second stage input (15) connectable to a second antenna port (7),- a first rectifying unit (12) connected to the first stage input (14) and connected to a first stage output (16),- a second rectifying unit (18) connected to the second stage input (15) and connected to a second stage output (17),- a trimming capacitor arrangement (30) connected to the first stage input (14) and connected to the second stage input (15), wherein the trimming capacitor arrangement (30) is electronically switchable to at least a first capacitance and to a second capacitance, and- a first auxiliary rectifier stage (71) connected to the first antenna port (6), the second antenna port (7), the first stage output (16) and to the second stage output (17) and coupled to the trimming capacitor arrangement (30) to switch the trimming capacitor arrangement (30) into a predefined auxiliary configuration.

The present invention concerns a debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), comprising a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

The invention relates to a switched resonant capacitor comprising a first capacitor and a second capacitor connected in series by means of a first switching element between a first conductor and a second conductor; the switched resonant capacitor further comprising a second switching element connected in parallel to the first capacitor and a third switching element connected in parallel to the second capacitor.