EM Microelectronic-Marin

The present disclosure relates to a system and a method for generating a compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, comprising temperature compensation data for the amplification of RF induced voltages.

The present disclosure relates to a system and a method for generating a temperature compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, comprising temperature compensation data for the amplification of RF induced voltages.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The present invention concerns a debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), comprising a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

In one aspect the present invention concerns a rectifier circuit (10) for a passive RFID circuit (1), the rectifier circuit (10) comprising:- at least a first rectifier stage (11) comprising a first stage input (14) connectable to a first antenna port (6) and comprising a second stage input (15) connectable to a second antenna port (7),- a first rectifying unit (12) connected to the first stage input (14) and connected to a first stage output (16),- a second rectifying unit (18) connected to the second stage input (15) and connected to a second stage output (17),- a trimming capacitor arrangement (30) connected to the first stage input (14) and connected to the second stage input (15), wherein the trimming capacitor arrangement (30) is electronically switchable to at least a first capacitance and to a second capacitance, and- a first auxiliary rectifier stage (71) connected to the first antenna port (6), the second antenna port (7), the first stage output (16) and to the second stage output (17) and coupled to the trimming capacitor arrangement (30) to switch the trimming capacitor arrangement (30) into a predefined auxiliary configuration.

An aspect of the invention describes a data reading system comprising two clock sources (CS1 and CS2), a configuration/access interface (C/A-I), and various logic and register modules. The system includes a configuration/access logic module (C/A-L) that receives signals from CS1 and interfaces with the data logic module (DL). The data register module (DR) stores data and provides it to a data output register module (DOR), which generates a data output signal. The system features a read window generator (RWG) and a read manager (RM) to manage reading operations. The system operates in an idle or reading state, controlling data flow based on the state of the configuration/access interface.

The invention relates to a switched resonant capacitor comprising a first capacitor and a second capacitor connected in series by means of a first switching element between a first conductor and a second conductor; the switched resonant capacitor further comprising a second switching element connected in parallel to the first capacitor and a third switching element connected in parallel to the second capacitor.

The present invention concerns an electronic circuit (10) for an optical motion sensing device (1), the electronic circuit comprising (10):- a processor (18) and a storage (16),- an image acquisition unit (11) configured to store a reference image (12) and a current image (13) to be compared with the reference image (12),- a correlation engine (14) connected to the image acquisition unit (11) and configured to determine a correlation coefficient between the reference image (12) and the current image (13) for each one of numerous displacements between the reference image (12) and the current image (13),- a search engine (15) connected to the correlation engine (14) and operable to compare the correlation coefficient of each displacement between the reference image (12) and the current image (13) with a predefined threshold correlation coefficient,- wherein the search engine (15) is operable in one of a preliminary search mode and an accurate search mode, wherein when in the accurate search mode, the search engine (15) is configured to store the correlation coefficient obtained from the correlation engine in the storage (16).

The present invention concerns a dual communication frequency RFID circuit (10) comprising:- a first logic unit (13) for processing data signals received or transmitted by a first frequency by a first antenna (11),- a second logic unit (14) for processing data signals received or transmitted by a second frequency by a second antenna (12),- a shared memory unit (15) connected to the first logic unit (13) and connected to the second logic unit (14) and comprising a shared password storage section (20) accessible by the first logic unit (13) and by the second logic unit (14).

The invention relates to a voltage limiter for a voltage regulator driving a digital or switching circuit, wherein the voltage limiter comprises a power input terminal connectable to the output of a voltage regulator; the voltage limiter further comprising a differential pair arrangement connected to a reference voltage input terminal and the power input terminal, an auxiliary differential mirror, an auxiliary load branch connecting the power input terminal to ground comprising an auxiliary load transistor device and wherein the voltage limiter is configured to activate the auxiliary load transistor device when the voltage at the power input terminal is larger than the voltage at the reference input terminal.