EM Microelectronic-Marin Patente

The present disclosure relates to a system and a method for generating a temperature compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, comprising temperature compensation data for the amplification of RF induced voltages.

The present disclosure relates to a system and a method for generating a compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, comprising temperature compensation data for the amplification of RF induced voltages.

In one aspect the present invention concerns a rectifier circuit (10) for a passive RFID circuit (1), the rectifier circuit (10) comprising:- at least a first rectifier stage (11) comprising a first stage input (14) connectable to a first antenna port (6) and comprising a second stage input (15) connectable to a second antenna port (7),- a first rectifying unit (12) connected to the first stage input (14) and connected to a first stage output (16),- a second rectifying unit (18) connected to the second stage input (15) and connected to a second stage output (17),- a trimming capacitor arrangement (30) connected to the first stage input (14) and connected to the second stage input (15), wherein the trimming capacitor arrangement (30) is electronically switchable to at least a first capacitance and to a second capacitance, and- a first auxiliary rectifier stage (71) connected to the first antenna port (6), the second antenna port (7), the first stage output (16) and to the second stage output (17) and coupled to the trimming capacitor arrangement (30) to switch the trimming capacitor arrangement (30) into a predefined auxiliary configuration.

An aspect of the invention describes a data reading system comprising two clock sources (CS1 and CS2), a configuration/access interface (C/A-I), and various logic and register modules. The system includes a configuration/access logic module (C/A-L) that receives signals from CS1 and interfaces with the data logic module (DL). The data register module (DR) stores data and provides it to a data output register module (DOR), which generates a data output signal. The system features a read window generator (RWG) and a read manager (RM) to manage reading operations. The system operates in an idle or reading state, controlling data flow based on the state of the configuration/access interface.

The present invention concerns a debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), comprising a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The invention relates to a switched resonant capacitor comprising a first capacitor and a second capacitor connected in series by means of a first switching element between a first conductor and a second conductor; the switched resonant capacitor further comprising a second switching element connected in parallel to the first capacitor and a third switching element connected in parallel to the second capacitor.

The present invention concerns an electronic circuit (10) for an optical motion sensing device (1), the electronic circuit comprising (10):- a processor (18) and a storage (16),- an image acquisition unit (11) configured to store a reference image (12) and a current image (13) to be compared with the reference image (12),- a correlation engine (14) connected to the image acquisition unit (11) and configured to determine a correlation coefficient between the reference image (12) and the current image (13) for each one of numerous displacements between the reference image (12) and the current image (13),- a search engine (15) connected to the correlation engine (14) and operable to compare the correlation coefficient of each displacement between the reference image (12) and the current image (13) with a predefined threshold correlation coefficient,- wherein the search engine (15) is operable in one of a preliminary search mode and an accurate search mode, wherein when in the accurate search mode, the search engine (15) is configured to store the correlation coefficient obtained from the correlation engine in the storage (16).

The present invention concerns a dual communication frequency RFID circuit (10) comprising:- a first logic unit (13) for processing data signals received or transmitted by a first frequency by a first antenna (11),- a second logic unit (14) for processing data signals received or transmitted by a second frequency by a second antenna (12),- a shared memory unit (15) connected to the first logic unit (13) and connected to the second logic unit (14) and comprising a shared password storage section (20) accessible by the first logic unit (13) and by the second logic unit (14).

The invention relates to a voltage limiter for a voltage regulator driving a digital or switching circuit, wherein the voltage limiter comprises a power input terminal connectable to the output of a voltage regulator; the voltage limiter further comprising a differential pair arrangement connected to a reference voltage input terminal and the power input terminal, an auxiliary differential mirror, an auxiliary load branch connecting the power input terminal to ground comprising an auxiliary load transistor device and wherein the voltage limiter is configured to activate the auxiliary load transistor device when the voltage at the power input terminal is larger than the voltage at the reference input terminal.

The present invention concerns an electronic circuit (5) and a method of sorting data elements provided in a memory array (20), wherein the memory array (20) comprises a number of memory areas (21, 22, 23, 24), each of which configured to store a data element (11, 12, 13, 14), the method comprises the steps of:- assigning a comparison counter (31, 32, 33, 34) to each data element (11, 12, 13, 14),- comparing a first data element (11) stored in a first memory area (21) with all further data elements (12, 13, 14) stored in the number of memory areas (22, 23),- incrementing a counter value of the comparison counter (31) of the first data element (11) if the comparison of the first data element (11) with any one of the further data elements (12, 13, 14) matches a predefined comparison condition, else incrementing the comparison counter of the other data element,- concurrently or sequentially comparing further data elements (12, 13...) with all subsequent data elements (13, 14...), and incrementing each associated counter value upon the success of the comparisons, in this way the counter value of all comparison counters (31, 32, 33, 34) of the respective data elements (11, 12, 13, 14) reflects the size of each data element of the memory array (20), in which respective data elements are actually stored, and- sorting the data elements (11, 12, 13, 14) on the basis of the comparison counters (31, 32, 33, 34).

The invention deals with a computer-implemented method for operating an electronic device comprising a microcontroller and an optical sensor generating flashes along an underlying surface, the method comprising steps for: - calculating a surface optical sensor flash rate, - generating surface flashes in order to acquire an associated image having pixels and identify surface characteristics along the underlying surface, - classifying surface characteristics comprising a method of comparing a ripple of the average light detected per pixel to a threshold.

The invention deals with a computer mouse and a computer-implemented method for operating a computer mouse comprising an optical sensor, the method comprising steps for:- calculating a first/tracking optical sensor flash rate,- generating tracking flashes in order identify relative displacement along an underlying surface,- calculating a second/surface optical sensor flash rate taking into account the first/tracking optical sensor flash rate,- generating surface flashes in order identify surface characteristics along the underlying surface, so that a surface flash is generated between two tracking flashes.

A computer-implemented method for operating a computer mouse comprising an optical sensor emitting flashes and calculating displacements, a communication module to communicate with a host MCU computer and one or more processors coupled to the optical sensor, the method comprising steps: - calculating an optical sensor flash rate by the host MCU computer, - triggering by the host MCU computer communication with the optical sensor in order to read the calculated displacement and triggers the next displacement calculation of the optical sensor to ask the optical sensor for the position at a time between two flashes.

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The present disclosure relates to a charge amplifier circuit (10) for a capacitive sensing arrangement (80), the charge amplifier circuit (10) comprising: - an first amplifier stage (20) comprising a first amplifier input (22), a second amplifier input (23) connectable to the capacitive sensing arrangement (80), and comprising a first amplifier output (24) and a second amplifier output (25), - a second amplifier stage (30) comprising a first amplifier input (32), a second amplifier input (33), a first amplifier output (34) and a second amplifier output (35), and - a switched capacitor arrangement (40) between the first amplifier stage (20) and the second amplifier stage (30), the switched capacitor arrangement (40) comprising a first integration capacitor (42), a second integration capacitor (43), a number of first switches (66, 67) and a number of second switches (68, 69).

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A method is provided for applying an illumination correction for an optical computer mouse. The method comprises the steps of: flashing (101) a light source of the mouse directed towards a surface; accumulating (103) voltage on a pixel array of the mouse to obtain raw pixel values of an image frame in response to detecting light reflected from the surface; applying (105) analog correction to the raw pixel values based on digital gain coefficients to obtain an array of corrected pixel values forming corrected image data; digitizing (109) the corrected image data with an analog-to-digital converter to obtain digital pixel values forming digital image data; and updating (111) the digital gain coefficients so that a respective gain coefficient corresponding to a respective digital pixel value is incremented if the respective digital pixel value is below or equal to a given pixel threshold value, and so that the respective gain coefficient corresponding to the respective digital pixel value is decremented if the respective digital pixel value is above the given pixel threshold value.

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