Leiterplattenanordnung für POTS-Splitter eines VDSL-Telekommunikationssystems

Details

Veröffentlichungs-Nr.

EP2418922

Aktenzeichen

EP10305853

Anmeldetag

2. August 2010

Veröffentlichung

3. April 2013

Erteilung

3. April 2013

Rechtsraum

EP

IPC

H05K1/02H04M7/16H04M11/06H04Q1/02

Abstract

The printed circuit board assembly for a POTS splitter comprises a printed circuit board PCB provided with one or more, e.g. 4, line interface connectors (X1 - X4) each connected to, e.g. n=12, low-pass filters (LPF1, LPR1; LPF2, LPR2; ... LPFn, LPRn) on the PCB. The line interface connectors are coupled to analog front end high-pass filters of the splitters on a line termination VDSL motherboard and so further to telecommunication lines towards Customer Premise Equipment CPE. To reduce the loading effect of each POTS splitter so that the Differential Mode Capacitance (Cdm1; Cdm2; ... Cdmn) of the line interface track towards the customer is smaller than 3pF, each low-pass filter is physically separated on the PCB into a front stage (LPF1; LPF2; ... LPFn) and a rear stage (LPR1; LPR2; ... LPRn). The front stage comprises at least one component of the low-pass filter, preferably the first inductor, and is connected and physically located on the PCB closer to the line interface connector (X1 - X4) than the rear stages.

Anmelder

Firma

Alcatel Lucent

Land

🇫🇷 Frankreich

Fachgebiete