Fehlermodusschaltungen

Details

Veröffentlichungs-Nr.

EP2541415

Aktenzeichen

EP11172202

Anmeldetag

30. Juni 2011

Veröffentlichung

1. Januar 2014

Erteilung

1. Januar 2014

Rechtsraum

EP

IPC

G06F11/267G01R31/3185

Abstract

Described herein is a test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits during each phase of manufacturing such as wafer-sort, wafer thinning, wafer stacking, and final packaging. The method comprises testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test and TSVs in close proximity and for connections between the TSV-under-test and another tier in the three-dimensional integrated circuit. A test circuit (400) comprises three switchable current paths connected to a power supply via a pull-up resistor (420) and a plurality of switches (Tx, Cx, Ax): a calibration path (ICALSENSE); a short path (ISHRSENSE); and a current measurement path (IFORCE). A power supply is connected to the measurement path (IFORCE), and the calibration path (ICALSENSE) and the short path (ISHRSENSE) are connected to ground via respective pull-down resistors (430, 440). For each TSV-under-test (TSV1), the desired mode of operation is selected by the closure of different combinations of switches (T1, C1, A1) and the current flowing through the pull-up resistor (420) in each mode of operation provides an indication of the whether the TSV-under-test (TSV1) has passed or failed the test.

Anmelder

Firma

IMEC

Land

🇧🇪 Belgien

Fachgebiete