Schreibkonfliktfreie, rauschtolerante Multiport-Bit-Zelle

Details

Veröffentlichungs-Nr.

EP2648187

Aktenzeichen

EP13161832

Anmeldetag

29. März 2013

Veröffentlichung

11. September 2019

Erteilung

11. September 2019

Rechtsraum

EP

IPC

G11C8/16G11C8/14G11C11/419G11C7/12G11C7/18

Abstract

A multi-port memory cell (112) of a multi-port memory array (104) includes a first inverter (206) that is disabled by a first subset (WWL0-3) of a plurality of write word lines and a second inverter (204), cross coupled with the first inverter (206), wherein the second inverter (204) is disabled by a second subset (WWL4-7) of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter (204). The second selection circuit has data inputs coupled to a second subset (WBL4-7) of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter (206).

Anmelder

Firmen

NXP USA, Inc.
Freescale Semiconductor, Inc.

Land

🇺🇸 USA

Fachgebiete