Potts, Susan Patricia

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Embodiments of semiconductor devices (200, 600, 700, 1100, 1300) and driver circuits (110) include a semiconductor substrate (210, 610, 710, 1110, 1310) having a first conductivity type, an isolation structure (including a sinker region (222, 622, 722, 1122, 1322, 1610, 1710) and a buried layer (220, 620, 720, 1120, 1320)), an active device within an area (230, 630, 730, 1130, 1330, 1520, 1620, 1720, 1820) of the substrate contained by the isolation structure, and a diode circuit (160). The buried layer is positioned below the top substrate surface (212, 612, 712, 1112, 1312), and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region (236, 636, 736, 1136, 1336) of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes (346, 446, 546, 1245, 1445) and/or PN junction diodes (846, 946, 1046, 1246, 1446, 1447). In further embodiments, the diode circuit may include one or more resistive networks (410, 510, 910, 1010) in series and/or parallel with the Schottky and/or PN diode(s).

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Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.

Embodiments of computer processing systems and methods are provided that include a memory protection unit (MPU) (60), and a plurality of region descriptors 62 associated with the MPU. The region descriptors include address range and translation identifier values for a respective region of memory. Control logic determines whether a translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, the control logic allows a first process being executed by the processing system to access a memory region allocated to a second process being executed by the processing system.

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