LDMOS-Anordnung mit hoher Durchbruchspannung

Details

Veröffentlichungs-Nr.

EP2680312

Aktenzeichen

EP13173277

Anmeldetag

21. Juni 2013

Veröffentlichung

25. März 2020

Erteilung

25. März 2020

Rechtsraum

EP

IPC

H01L29/78H01L29/10H01L21/336// H01L29/06

Abstract

A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

Anmelder

Firmen

NXP USA, Inc.
Freescale Semiconductor, Inc.

Land

🇺🇸 USA

Fachgebiete