Dünnschichttransistormatrixanordnung

Details

Veröffentlichungs-Nr.

EP2752879

Aktenzeichen

EP14150176

Anmeldetag

3. Januar 2014

Veröffentlichung

18. Oktober 2023

Erteilung

18. Oktober 2023

Rechtsraum

EP

IPC

H01L29/417H01L27/12

Abstract

A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.

Anmelder

Firma

Samsung Display Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete