Verfahren zur Herstellung einer JFET Halbleitervorrichtung und JFET Halbleitervorrichtung

Details

Veröffentlichungs-Nr.

EP2782122

Aktenzeichen

EP14160755

Anmeldetag

19. März 2014

Veröffentlichung

27. Februar 2019

Erteilung

27. Februar 2019

Rechtsraum

EP

IPC

H01L21/337H01L29/808

Abstract

A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n + -type source layer on a surface of an n - -type drift layer formed on an n + -type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n - -type drift layer with a silicon oxide film formed on the n - -type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n - -type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n - -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Anmelder

Firma

Renesas Electronics Corporation

Land

🇯🇵 Japan

Fachgebiete