Hybrides MDLL/PLL-Design mit gleichförmig verteilten Ausgangsphasen

Details

Veröffentlichungs-Nr.

EP2903162

Aktenzeichen

EP15152877

Anmeldetag

28. Januar 2015

Veröffentlichung

7. April 2021

Erteilung

7. April 2021

Rechtsraum

EP

IPC

H03L7/081H03L7/099

Abstract

A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL.

Anmelder

Firma

Samsung Display Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete