Steuerungsschaltungen, Datenschnittstellenblöcke und Verfahren zur Übertragung von Daten

Details

Veröffentlichungs-Nr.

EP2940575

Aktenzeichen

EP14176349

Anmeldetag

9. Juli 2014

Veröffentlichung

9. Mai 2018

Erteilung

9. Mai 2018

Rechtsraum

EP

IPC

G06F5/06G06F13/12G06F13/42G06F9/30G06F9/38

Abstract

A processor circuit, with: - a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words; - a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.

Anmelder

Firma

NXP B.V.

Land

🇳🇱 Niederlande

Fachgebiete