Hardingham, Christopher Mark

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

An apparatus and method for synchronizing a reference oscillator. A frequency of an adjustable frequency reference oscillator is adjusted based on an indication that radio signal processing is inactive and based on a phase error between a synchronized frequency reference signal and a frequency based on a synchronization reference signal. The adjustable frequency reference oscillator provides the synchronized frequency reference signal for a radio frequency circuit and a timing signal indicates whether radio signal processing by a radio frequency circuit is active or inactive. Adjustment of the frequency of the adjustable frequency reference oscillator is inhibited based on the timing signal indicating that radio signal processing is active.

First antennas in a first radar sensor receive first signals transmitted by one or more second antennas in a second radar sensor and reflected by at least one object. Third antennas in the second radar sensor receive second signals transmitted by one or more fourth antennas in the first radar sensor and reflected by the at least one object. A snapshot that includes complex values that represent phase responses of the first signals and the second signals is generated and a carrier phase offset between the first signals and the second signals is estimated based on the snapshot. In some cases, an output representing detection of an object is generated based on the carrier phase offset.

A method, system, and apparatus for bandsteering a client station to an access point. A non-6 GHz AP receives a plurality of probe requests from the client station and determines that the client station is operable to communicate with the 6 GHz AP based on an indication in the probe requests. A threshold estimated number of probe requests transmitted by the client station is ignored to bandsteeer the client station to connect to the 6 GHz AP based on the determination where the threshold is based on a number of probe requests transmitted by the client station in a scan cycle. A probe response is then transmitted after the threshold estimated number of the probe requests are transmitted by the client station, wherein the client station is allowed to connect to the non-6 GHz AP.

A memory includes a data array divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns. A column decoder selects one column from each IO group to provide selected data lines, and one column from the redundant group to provide a redundant data line. Repair circuitry, during normal operation, performs column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups. Read/write circuitry, in response to a read access during a test mode, outputs read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines. Control circuitry, in response to the read access during the test mode, provides the output read data sensed from the redundant data line external to the memory via a memory output pin.

A radio frequency amplifier device includes four power amplifiers. The first power amplifier output is coupled through a first inductive element to a first signal output terminal and through a second inductive element to a first shunt circuit access terminal. The second power amplifier output is coupled through a third inductive element to the first shunt circuit access terminal. The third power amplifier output is coupled through a fourth inductive element to a second signal output terminal and through a fifth inductive element to a second shunt circuit access terminal. The fourth power amplifier output is coupled through a sixth inductive element to the second shunt circuit access terminal. A first output combiner circuit includes the second and third inductive elements, and a second output combiner circuit includes the fifth and sixth inductive elements. External shunt capacitors are coupled to the first and second shunt circuit access terminals.

Systems and methods for delta-sigma modulators with downsampled digital integrators. In various embodiments, a delta-sigma modulator may include: a comparator configured to receive an analog input and to provide a digital output at a sampling frequency, where the digital output is applied to an integrator path and to a feed-forward path; a digital integrator in the integrator path, where the digital integrator is configured to operate with a clock frequency that is less the sampling frequency; and a summer configured to add an output of the integrator path to an output of the feed-forward path to produce a bitstream.

A method is proposed to make more efficient use of limited computing resources in signature generation.

The disclosure relates to a supply voltage glitch detection circuit (300) comprising: a first flip-flop (301) having a data input (302), a clock input (303) and an output (304); a delay circuit (305) having an output (307) connected to the data input of the first flip-flop; a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to an input (306) of the delay circuit (305); a second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop, wherein the circuit (300) is configured to cause a glitch detection signal output to change state upon a supply voltage of the circuit (300) deviating to cause a change in a delay provided by the delay circuit (305).

An apparatus comprising: a controller configured to control transmission by a Distributed Coherent Radar, DCR, system and a processor configured to process radar signals received by the DCR system;wherein the controller is configured to provide for transmission of a first chirp from a plurality of transmit antennas of a first radar head of the DCR system, and from a first predetermined antenna in a first band and by a second predetermined antenna of a second head in a second band; and provide for transmission of a second chirp from a plurality of transmit antennas of the second radar head, the second predetermined antenna in a fourth band and by the first predetermined antenna in third band; andthe processor is configured to, based on the received signals, determine a phase-noise estimation.