Abtast- und Halteschaltung für einen verschachtelten Analog-Digital-Wandler

Details

Veröffentlichungs-Nr.

EP2977989

Aktenzeichen

EP14178665

Anmeldetag

25. Juli 2014

Veröffentlichung

8. Mai 2019

Erteilung

8. Mai 2019

Rechtsraum

EP

IPC

G11C27/02H03M1/12

Abstract

The present invention relates to a sample-and-hold circuit (1) comprising - a transistor (11) arranged for switching between a sample mode and a hold mode, - a bootstrap circuit (2) arranged for maintaining in said sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in said hold mode, said bootstrap circuit comprising a bootstrap capacitance (21) arranged for being precharged to a given voltage during said hold mode, said bootstrap capacitance being connected between the source terminal and the gate terminal during said sample mode, characterised in that the bootstrap circuit comprises a switched capacitor charge pump (22) for generating that given voltage.

Anmelder

Firma

IMEC VZW

Land

🇧🇪 Belgien

Fachgebiete