Patent Department IMEC

Disclosed is a two-electrode device, such as a Josephson junction or a capacitor, comprising top and bottom electrodes (18, 27) formed of superconducting NbTiN which are separated by a non-superconducting interlayer (17), wherein the bottom electrode is larger than the interlayer and the top electrode. The electrodes and the interlayer are formed by two separate patterning steps and embedded in an enveloping dielectric material (25, 28, 35) that is subsequently planarized by a first CMP stopping on the upper surface of the top electrode (18), thereby forming a first planarized surface (36). Thereafter, a via opening (39) is formed, exposing the upper surface of the bottom electrode (27), filled with an electrically conductive material (40), and planarized by a second CMP. Wiring conductors (57, 58) are then formed on the second planarized surface (36').

Example embodiments describe a computer-implemented methods for training a spiking neural network for encoding and decoding event information obtained from a set of sensors in an array-based sensing system. Further embodiments describe a neural network training system as well as a sensor and an edge gateway device employing such encoding and decoding spiking neural networks.

A Gallium-Nitride inverter is disclosed using only n-type enhancement mode transistors, thereby achieving Direct-Coupled-FET (DCFL) logic.

The invention is related to a micro-electronic component comprising superconducting digital logic circuitry, including at least one capacitor that comprises a bottom and top electrode (6',8') formed of superconducting NbTiN, and a dielectric interlayer (7') formed of orthorhombic HZO. A method for producing the capacitor includes method steps for producing of NbTiN electrodes defined by atomic concentrations of its constituent elements which enable superconductivity as well as the formation of HZO in the orthorhombic phase that remains stable throughout the sequence of method steps for producing the capacitor. The invention thereby enables producing capacitors for integration in an SDL circuit, for example to be used for the power supply in the circuit, which exhibit superior electrical performance combined with advanced scalability to nanosized dimensions.

A thinned semiconductor substrate (1) is provided having a front end of line (FEOL) portion (2) on its front side. The FEOL portion includes conductive structures (3,40) at the front side of the thinned substrate, which need to be contacted by connections through the substrate. An opening (15) is etched from the back of the thinned substrate, to be filled with a conductive material. The bottom of said opening overlaps at least partially the end surface (14) of the conductive structure to be contacted, and further overlaps one or more portions of semiconductor material of the substrate. According to the invention, etching of the opening continues beyond the end surface into said semiconductor portion(s), to thereby create one or more cavities (27). A first dielectric layer (30) is formed on the sidewalls and bottom of the opening, so that the cavity or cavities are filled with the material of the first layer. This material is then removed everywhere except in the cavity or cavities (27). If necessary, a second dielectric layer (31) may be formed as a liner on the sidewalls and bottom of the opening (15), to be opened up at the bottom by an anisotropic etch to thereby expose said end surface (14), but wherein the dielectric of the first layer remains in the cavity or cavities (27). These dielectric-filled cavities thereby inhibit the formation of shorts between the eventual through-connection (18,43) obtained by filling the opening, and the semiconductor material of the substrate (1)..

According to the method of the invention, a trench (10) is formed in a semiconductor layer (1) of a device wafer for the fabrication of ICs, followed by the deposition of a liner (11) on the sidewalls of the trench. The liner is removed from the bottom of the trench, and the trench may be deepened anisotropically to form an extension (12) of the trench. This may be done along the full length of the trench, or locally by applying a mask. An etch process is then applied wherein the semiconductor material is removed outwardly from the extension, thereby creating a cavity (13) that is wider than the trench. The etch process is selective relative to the liner (11), so that the cavity is formed essentially below the liner (11). Then the combined space formed by the trench and the cavity is filled with an electrically conductive material, possibly after forming a second liner (14). This results in the formation of a buried interconnect rail (15) comprising a narrow portion (15a) in the area of the trench and a wider portion (15b) in the area of the cavity. The wider portion may be contacted from the back side of the semiconductor layer by a TSV connection (24), enabling a large contact area between said TSV connection and the buried rail. The selectivity of the etch process applied for forming the cavity (13) results in the formation of the cavity (13) and thereby of the wider rail portion (15b) at a location that is remote from the active devices formed on the front surface of the semiconductor layer (1).

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