Patent Department IMEC

In a quantum dot device according to the invention, a plurality of gates (1,2) is provided on a gate dielectric layer (4) formed on a semiconductor substrate (3) configured to confine qubits in well-defined quantum dots. Via connections (10,18) which are directly contacting the gates include at least one or more via connections formed of an electrically conductive ferromagnetic material, whereas the via connections which are contacting the remaining gates are not formed of a ferromagnetic material. Also, the material of the gates (1,2) is electrically conductive but not ferromagnetic. The invention thereby enables addressing and controlling individual qubits associated to gates contacted by ferromagnetic via connections (10) which are configured to act as permanent magnets in the operative quantum dot device.

A stack of alternatingly applied etch stop layers (27) and mask layers (28) is produced on a target layer (25) present on a support substrate (26). The target layer is to be patterned according to a pattern comprising parallel line features (34,34'). The top mask layer is patterned according to a pattern of openings (30) and thereafter these openings are elongated by directional etching relative to the etch stop layer, to form a pattern of elongated openings (31,31'). This pattern is transferred to the subsequent mask layer (28) and in said subsequent mask layer, the elongated openings are further elongated by directional etching. This sequence is repeated down to the bottom mask layer. In said bottom mask layer, the pattern of openings has been elongated to a set of lines (34,34'), which are then transferred to the target layer. By repeating the elongation process a number of times, the obtainable elongation is increased compared to a process wherein only one directional etch step is applied.

The method comprises the steps of producing a stack of at least two layers (30,31,32) on a support substrate (25), by lithography and anisotropic etching, producing an opening (33) through said stack of at least two layers, and thereafter applying at least a first directional etching process step, using an etch beam configured to remove the material of one or more upper layers (32) of the stack selectively with respect to the layer or layers (30,31) directly underneath said one or more upper layers, to thereby enlarge the opening in the one or more upper layers (32) while essentially maintaining the in-plane dimensions of the opening in the layer or layers (30,31) directly underneath the one or more upper layers (32). The method can be applied to a stack of several layers which can be enlarged stepwise with respect to further underlying layers of the stack. Directional etching can be done in two opposite directions, possibly applying different etch chemistries in the two directions, to thereby enable the creation of complex three-dimensional structures without requiring expensive multiple lithography steps.

A pattern is produced in a die area (25) of a layer (30,33) formed on a support substrate (32) by at least two process sequences, each comprising a lithography step and an etch step, performed in adjacent subportions of the die area. One or more parallel line shaped features (28) of the pattern extend from the first subportion (25a) of the die area to the second subportion (25b), i.e. across the border (27) between the die areas. Mutually aligned and spaced apart first and second parts of the line features are printed in the respective process sequence steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e. in the form of trenches (28'a,28'b) in the layer or in the form of lines separated by mutually aligned trenches (37a;37b). In either case, directional etching is thereafter applied to stretch the aligned trenches and thereby obtain the desired line features (28) extending from one subportion of the die area to the other subportion.

A layer (28) is produced on an etch stop layer (27) formed on a support substrate. The layer is patterned by forming at least one opening (30) having upright sidewalls through the full thickness of the layer. The opening is enlarged by a sequence of directional etch steps wherein the angle of incidence of the applied plasma beam (8) is increased at every subsequent step compared to the previous step, so that the plasma beam impinges on the full height of the sidewall of the opening (30) or enlarged opening (31) at every step. Subsequent directional etch steps can be performed in the same scanning direction at each step, or the scanning direction can be changed at every step or combinations of equal and differing scanning directions can be applied, enabling thereby to obtain various shapes of pattern features. The adjustment of the angle of incidence enables a higher etch rate in the scanning direction and thereby a higher obtainable elongation compared to methods wherein repeated directional etch steps are performed applying he same angle of incidence at each step.

Disclosed is a two-electrode device, such as a Josephson junction or a capacitor, comprising top and bottom electrodes (18, 27) formed of superconducting NbTiN which are separated by a non-superconducting interlayer (17), wherein the bottom electrode is larger than the interlayer and the top electrode. The electrodes and the interlayer are formed by two separate patterning steps and embedded in an enveloping dielectric material (25, 28, 35) that is subsequently planarized by a first CMP stopping on the upper surface of the top electrode (18), thereby forming a first planarized surface (36). Thereafter, a via opening (39) is formed, exposing the upper surface of the bottom electrode (27), filled with an electrically conductive material (40), and planarized by a second CMP. Wiring conductors (57, 58) are then formed on the second planarized surface (36').

Example embodiments describe a computer-implemented methods for training a spiking neural network for encoding and decoding event information obtained from a set of sensors in an array-based sensing system. Further embodiments describe a neural network training system as well as a sensor and an edge gateway device employing such encoding and decoding spiking neural networks.

A Gallium-Nitride inverter is disclosed using only n-type enhancement mode transistors, thereby achieving Direct-Coupled-FET (DCFL) logic.

The invention is related to a micro-electronic component comprising superconducting digital logic circuitry, including at least one capacitor that comprises a bottom and top electrode (6',8') formed of superconducting NbTiN, and a dielectric interlayer (7') formed of orthorhombic HZO. A method for producing the capacitor includes method steps for producing of NbTiN electrodes defined by atomic concentrations of its constituent elements which enable superconductivity as well as the formation of HZO in the orthorhombic phase that remains stable throughout the sequence of method steps for producing the capacitor. The invention thereby enables producing capacitors for integration in an SDL circuit, for example to be used for the power supply in the circuit, which exhibit superior electrical performance combined with advanced scalability to nanosized dimensions.

A thinned semiconductor substrate (1) is provided having a front end of line (FEOL) portion (2) on its front side. The FEOL portion includes conductive structures (3,40) at the front side of the thinned substrate, which need to be contacted by connections through the substrate. An opening (15) is etched from the back of the thinned substrate, to be filled with a conductive material. The bottom of said opening overlaps at least partially the end surface (14) of the conductive structure to be contacted, and further overlaps one or more portions of semiconductor material of the substrate. According to the invention, etching of the opening continues beyond the end surface into said semiconductor portion(s), to thereby create one or more cavities (27). A first dielectric layer (30) is formed on the sidewalls and bottom of the opening, so that the cavity or cavities are filled with the material of the first layer. This material is then removed everywhere except in the cavity or cavities (27). If necessary, a second dielectric layer (31) may be formed as a liner on the sidewalls and bottom of the opening (15), to be opened up at the bottom by an anisotropic etch to thereby expose said end surface (14), but wherein the dielectric of the first layer remains in the cavity or cavities (27). These dielectric-filled cavities thereby inhibit the formation of shorts between the eventual through-connection (18,43) obtained by filling the opening, and the semiconductor material of the substrate (1)..