Verfahren zur Vereinzelung eines Stapels von Halbleiterwafern

Details

Veröffentlichungs-Nr.

EP3171399

Aktenzeichen

EP15195145

Anmeldetag

18. November 2015

Veröffentlichung

3. Juni 2020

Erteilung

3. Juni 2020

Rechtsraum

EP

IPC

H01L21/683H01L21/768H01L21/78H01L23/48H01L25/065H01L21/98

Abstract

According to the method of the invention, a plurality of wafers, each comprising a plurality of integrated circuit dies, are bonded to form a stack of wafers. In this stack, the dies are bonded together by direct bonding techniques as known in the art. According to the invention, prior to each bonding step, singulation streets are produced along the circumference of two dies that are to bonded, to the extent that in the singulation streets, all materials of the dies are removed from the two surfaces that are to be bonded except the semiconductor substrate portion of the dies. This is preferably done by a litho and etch step, etching down through the materials until reaching the substrate portion. Singulation streets on directly bonded surfaces are mutually aligned in the bonding steps, and all singulation streets in the stack are equally aligned to each other. An additional singulation street, aligned with the earlier produced singulation streets, is produced on the top layer of the stack, after production of contact structures such as bumps or pillars. Separation of a stack of dies from the wafer stack is achieved by an etch step, removing the material of the substrates of the stack, in the area corresponding to the aligned singulation streets.

Anmelder

Firma

IMEC VZW

Land

🇧🇪 Belgien

Fachgebiete