Dtc-Basierter Phasenregelkreis und Verfahren zum Betreiben des Dtc-Basierten Phasenregelkreises

Details

Veröffentlichungs-Nr.

EP3249817

Aktenzeichen

EP17172898

Anmeldetag

24. Mai 2017

Veröffentlichung

26. Dezember 2018

Erteilung

26. Dezember 2018

Rechtsraum

EP

IPC

H03L7/197H03L7/081H03L7/099

Abstract

The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a stream of pseudo-random offsets, i.e. pseudo-random numbers, to the delay value. The offset is such that the target output of the phase detector remains substantially unchanged.

Anmelder

Firmen

IMEC vzw
Stichting IMEC Nederland
Vrije Universiteit Brussel

Land

🇧🇪 Belgien

Fachgebiete