Hardware-Beschleuniger-Architektur und -Template zum K-Means-Clustering auf Webebene

Details

Veröffentlichungs-Nr.

EP3343392

Aktenzeichen

EP17207532

Anmeldetag

14. Dezember 2017

Veröffentlichung

10. November 2021

Erteilung

10. November 2021

Rechtsraum

EP

IPC

G06F17/16G06F16/22G06F16/28G06N20/00

Abstract

Hardware accelerator architectures for clustering are described. A hardware accelerator includes sparse tiles and very/hyper sparse tiles. The sparse tile(s) execute operations for a clustering task involving a matrix. Each sparse tile includes a first plurality of processing units to operate upon a first plurality of blocks of the matrix that have been streamed to one or more random access memories of the sparse tiles over a high bandwidth interface from a first memory unit. Each of the very/hyper sparse tiles are to execute operations for the clustering task involving the matrix. Each of the very/hyper sparse tiles includes a second plurality of processing units to operate upon a second plurality of blocks of the matrix that have been randomly accessed over a low-latency interface from a second memory unit.

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Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete