Samson & Partner Patentanwälte mbB

Camera tuning process is a time consuming and labor-intensive process. To address this issue, camera tuning system including a multi-modal large language model and a retrieval-augmented generation system can be implemented to intelligently and efficiently handle a camera tuning task in real-time. The multi-modal large language model can evaluate image quality and can be finetuned using high-quality labeled data and synthetically generated labeled data. The retrieval-augmented generation system can incorporate camera configuration knowledge into a vector database and can leverage a retrieved context to generate a configuration solution that addresses image quality issues identified by the multi-modal large language model. The resulting camera tuning system is a unified process that can identify image quality issues and provide configuration solutions that address both technical and aesthetic image quality concerns.

Integrated circuit (IC) devices having isolation structures in metal gate cuts. An IC device may include first and second source-drain contacts in first and second transistor structures over a substrate, and a dielectric structure having first and second feet extending into the substrate, between the first and second source or drain contacts, and with a portion of the substrate between the first and second feet. The first and second feet may each have a width approximately equal to a gate length. The portion of the substrate between the first and second feet of the dielectric structure has a width approximately equal to a distance between adjacent gate electrodes. The dielectric structure may be formed in a gate cut by a self-aligned etch following a selective recess of source-drain contacts.

Integrated circuit (IC) devices having gate-all-around (GAA) transistors. An IC device may include adjacent GAA transistors with gate electrodes having different gate dielectric stacks separated by a dielectric wall. The gate dielectric stacks may include inner gate dielectric layers on nanoribbon channels and outer gate dielectric layers on the inner gate dielectric layers. The inner gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The outer gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The dielectric wall between gate electrodes and gate dielectric stacks may enable independent processing of the transistors gates by dividing the nanoribbon channels into separate gate tubs.

Semiconductor devices and systems with a protective diode cap, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a fin, p-type and n-type epitaxial structures over the fin, and a dielectric liner under the fin, where the dielectric layer does not include oxygen.

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor. Each have a stack of nanowires contacted by source and drain structures at opposite ends of the nanowires. The nanowires of the n-type transistor have a layer including lanthanum on the nanowires, and the nanowires of the p-type transistors are absent the layer including lanthanum. The gate structures of the n-type transistor and the p-type transistor have the same gate dielectric, work function metal, and bulk metal.

Architectures and methods for differential CMOS contact profiles. Architectures include a CMOS isolation layer with a plurality of negative metal oxide semiconductor (NMOS) regions and a plurality of positive metal oxide semiconductor (PMOS) regions. The NMOS regions have a respective NMOS contact characterized by a first cavity formed in an upper surface of the isolation layer, extending orthogonally into the NMOS region to a first depth, and filled with a conductive material. The PMOS regions have a respective PMOS contact characterized by a second cavity formed in the upper surface of the isolation layer, extending orthogonally into the PMOS region to a second depth, and filled with the conductive material. The first depth is more than four times the second depth.

Techniques are provided herein to form semiconductor devices with thermal management structures designed to provide additional heat dissipation paths. A semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. In one example, a subfin region beneath the semiconductor region is removed and replaced with a material having a thermal conductivity of at least 1.5 W/m·K. In another example, a material layer is formed between conductive contacts on the top surfaces of the source and drain regions that has a thermal conductivity of at least 1.5 W/m·K. In another example, the conductive contacts extend through at least 50% of an entire height of the source and drain regions to provide an enhanced thermal path. Any of the above-mentioned structures may also be combined in one or more devices to provide multiple different thermal management structures.

Described herein are nanoribbon transistors with lined cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a liner layer next to the gate stack, and a fill material nested within the liner layer and adjacent to the source or drain. The liner layer is a non-oxide dielectric. For example, the liner may be a low-k nitride. The liner layer may be conformally deposited, and a portion of the liner layer may extend between the gate stack and the source or drain. Using a non-oxide material prevents removal of the liner during an oxide clean step prior to nanoribbon release.

Described herein are nanoribbon transistors and processes for forming nanoribbon transistors that include a nitride liner to protect the channel material during an oxide anneal. An oxide may be used to fill trenches between stacks of nanoribbons; the oxide is annealed, and then the oxide is recessed, forming isolation regions. Source and drain regions are formed over the isolation regions. In the resulting devices, the isolation regions have a liner layer that includes nitrogen. An additional oxide liner may be around the nitride liner.

Systems and methods are provided for a neural network for frame interpolation. The systems and methods can be used in real time applications such as gaming platforms, and include receiving two consecutive input image frames and a motion vector, and warping the input image frames to generate an intermediate frame at a new timepoint that lies between the two input image frames. A first network generates optical flow data representing changes between the two consecutive input image frames, such as changes in illumination and/or shading. The system generates optical flow data from each input image frame to the new timepoint as well as motion vectors from each input image to the new timepoint. A second network can use the optical flow data and the motion vector data to generate the intermediate frame. The frame interpolation pipeline can generate intermediate frames in an interactive environment where future frames are unknown.