Samson & Partner Patentanwälte mbB

A processor power limit control scheme that controls the processor power limit value based on a monitored system power for a compute platform that includes the processor.

A method for performing biometric identity validation to confirm identity of a user. The method comprises providing a mobile application configured to be executed on a device of the user, to: register an enrolment data in respect of the user, for enrolling the user for biometric identity validation; when the user device is in proximity of one or more biometric touchpoint devices, enable pairing between the user device and the one or more biometric touchpoint devices to establish, with each of the one or more biometric touchpoint devices, a respective data connection between the user device and the biometric touchpoint devices, the one or more biometric touchpoint devices each comprising a biometric camera. In response to the user presenting at any one of the one or more biometric touchpoint devices to be processed thereby, and the biometric touchpoint device capturing a live image data of the user, the captured live image data is processed to obtain a live biometric data, and a data transfer is enabled to transfer at least the live biometric data or a reference biometric data obtained from the enrolment data, between the biometric touchpoint device that captured the live image data and the device of the user via the established data connection. The identity of the user is confirmed based on a result of a match between the live biometric data and the reference biometric data.

A method and system for deploying a natural language (NL) virtual interaction profile in a dynamic transaction management environment are disclosed. The system includes an Al engine configured to generate virtual electronic profiles based on training datasets of NL dialogue sequences between client devices and agent terminals. The virtual profiles simulate interaction behaviors, enabling iterative dialogues with agent terminals in response to dynamically changing transaction variables. By setting a target number of iteration cycles, the method aims to align interactions with predefined efficiency thresholds, reducing redundant access to transaction management engines and optimizing computational resource allocation. The disclosed system enhances processing efficiency within complex multi-component networks by streamlining interactions and minimizing unnecessary communication cycles.

Examples include techniques to manage data sharing for a multi-core processor. The examples include use of a data sharing counter value to determine whether to cause a last level cache (LLC) slice allocated to a core of the multi-core processor to be placed in an inclusive or non-inclusive mode for other cores of the multi-core processor to access data loaded to the LLC slice.

A method for operating a touchpoint, the method comprising a biometric authentication system: receiving authentication biometric data; associating the authentication biometric data with a person; obtaining a pre-computed risk score associated with the person; determining whether the risk score exceeds an authentication risk threshold; operating the touchpoint to perform biometric authentication using the authentication biometric data in the event that the pre-computed risk score does not exceed the authentication risk threshold; and operating the touchpoint with an enhanced authentication routine in the event that the pre-computed risk score exceeds the authentication risk threshold.

Techniques for tag checking for dynamically repeating memory accesses are described. In an embodiment, an apparatus includes instruction decoder circuitry to decode a single instruction, the single instruction having a format including an opcode field, the single instruction having a first opcode value in the opcode field; and execution circuitry coupled to the instruction decoder circuitry, the execution circuitry to perform operations in response to decoding of the single instruction, the operations including performing repeating memory tag checking operations in connection with repeating memory access operations.

An apparatus and method including: graphics processing cores to execute a mesh shader to process a triangle list associated with a mesh and generate a corresponding tristrip; clipper circuitry to clip the tristrip to a view volume, the clipper circuitry to: read corresponding header data including render target array index (RTAI) and view port index (VPI) values corresponding to a current vertex of the tristrip; perform a vertex cache lookup to determine corresponding RTAI and VPI values associated with a previously processed vertex, if any; read vertex data corresponding to the current vertex from memory and processing with new VPI and RTAI values when the RTAI and VPI values of the current vertex do not match those of a previously processed vertex; and perform clip operations based on previously processed vertex data when the RTAI and VPI values of the current vertex match those of the previously processed vertex.

A processor or other apparatus of an aspect includes a cache to store cache lines and a circuitry coupled with the cache. The circuitry is to receive a memory access request for data at a memory address from a first security domain. The data at the memory address is to be shared by a plurality of security domains including the first security domain. A side-channel protection is to be used for the data. The circuitry is to implement the side-channel protection for the data. This includes not providing a cache line corresponding to the memory address from the cache to the first security domain, when the cache line exists in the cache and is valid, if the first security domain has not previously accessed the cache line in the cache. Other processors, methods, systems, and instructions are disclosed.

An example processor executes an instruction having an operand field to indicate a multi-register cross-product matrix multiplication to be performed with the first plurality of sub-matrices and the second plurality of sub-matrices to generate the third plurality of sub-matrices. Execution circuitry execute the instruction, the execution circuitry to generate each sub-matrix of the third plurality of sub-matrices in a corresponding vector register of the third plurality of vector registers by multiplying a sub-matrix in a corresponding vector register of the first plurality of vector registers and a sub-matrix in a corresponding vector register of the second plurality of vector registers.

An example processor includes vector registers to store sub-matrices of two source matrices and execution circuitry to perform a cross-product matrix multiplication. A decoder interprets an instruction specifying the source matrices and the operation. The execution circuitry multiplies each combination of sub-matrices from the two source matrices-first with first, first with second, second with first, and second with second-to generate four corresponding sub-matrices of a result matrix, which are stored in a third vector register. This architecture enables efficient parallel matrix computations for high-performance processing tasks.