Herstellung eines Mos-Transistors auf der Basis eines 2D-Halbleitermaterials

Details

Veröffentlichungs-Nr.

EP3404723

Aktenzeichen

EP18172456

Anmeldetag

15. Mai 2018

Veröffentlichung

31. März 2021

Erteilung

31. März 2021

Rechtsraum

EP

IPC

H01L29/778H01L21/336H01L29/417// H01L29/16H01L29/24

Abstract

The invention relates to a method for manufacturing a MOS transistor, comprising: a) forming a first conductive or semiconductive layer (105); b) forming a sacrificial gate on the first layer, and a second layer (111) made of an insulating material laterally surrounding the sacrificial gate; c) forming, on either side of the sacrificial gate, electrical connection elements (115) for source and drain passing through the second layer (111) and coming into contact with the first layer (105); d) removing the sacrificial gate and the portion of the first layer (105) located directly above the sacrificial gate; e) depositing a third layer (119) made of a two-dimensional semiconductor material; f) depositing a fourth layer (121) made of an insulating material on the third layer (119); and g) forming a conductive gate (123) in the opening (117), on the fourth layer (121).

Anmelder

Firma

Commissariat à l'Energie Atomique et aux Energies Alternatives

Land

🇫🇷 Frankreich

Fachgebiete