Gate für einen Selbstsperrenden Transistor

Details

Veröffentlichungs-Nr.

EP3442026

Aktenzeichen

EP17186014

Anmeldetag

11. August 2017

Veröffentlichung

8. März 2023

Erteilung

8. März 2023

Rechtsraum

EP

IPC

H01L29/10H01L29/36H01L21/205// H01L29/778H01L29/20

Abstract

A method for forming a gate of an enhancement-mode transistor comprising: a. providing a p-doped Al x Ga y In z N gate layer (2), consisting of a first (2a) and a second part (2b) on top of one another, above a p-doped Al x' Ga y' In z' N channel layer (4) of an enhancement-mode transistor under construction, and b. providing a metal gate layer (1) on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped Al x Ga y In z N gate layer comprises the steps of: a1. growing the first part above the p-doped Al x' Ga y In z' N channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3x10 19 atoms/cm 3 and a2. growing a second part having an average Mg concentration higher than 3x10 19 atoms/cm 3 and having a top surface having a Mg concentration higher than 6x10 19 atoms/cm 3 , on the first part.

Anmelder

Firma

IMEC vzw

Land

🇧🇪 Belgien

Fachgebiete