Halbleiterintegrierte Schaltvorrichtung und Datenvergleichsverfahren

Details

Veröffentlichungs-Nr.

EP3457292

Aktenzeichen

EP18186793

Anmeldetag

1. August 2018

Veröffentlichung

7. Oktober 2020

Erteilung

7. Oktober 2020

Rechtsraum

EP

IPC

G06F13/32G06F11/16

Abstract

Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.

Anmelder

Firma

Renesas Electronics Corporation

Land

🇯🇵 Japan

Fachgebiete