Speicherarchitektur mit Reaktionsmanager für Fehlerkorrekturschaltung

Details

Veröffentlichungs-Nr.

EP3477478

Aktenzeichen

EP18201756

Anmeldetag

22. Oktober 2018

Veröffentlichung

30. November 2022

Erteilung

30. November 2022

Rechtsraum

EP

IPC

G06F11/10H04L1/00

Abstract

A memory (58) includes error correction circuitry that receives a data packet (51), outputs a correctable error flag (55) indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag (57) indicating presence or absence of an uncorrectable error in the data packet. A response manager (60), operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

Anmelder

Firmen

STMicroelectronics International N.V.
STMicroelectronics S.r.l.

Land

🇳🇱 Niederlande

Fachgebiete