Überlebensfähigkeitsgarantien für den Speicherdatenverkehr

Details

Veröffentlichungs-Nr.

EP3547150

Aktenzeichen

EP19159850

Anmeldetag

27. Februar 2019

Veröffentlichung

4. November 2020

Erteilung

4. November 2020

Rechtsraum

EP

IPC

G06F13/16G06F9/50G06F11/30G06F3/06H04L12/825H04L12/801H04L12/26G06F11/07G06F11/34H04L12/815H04L12/841

Abstract

Various systems and methods for controlling memory traffic flow rate are described herein. A system (300A) for computer memory (306A, 306B) management, the system comprising: rate control circuitry (312) to: receive a rate exceeded signal from monitoring circuitry (310), the rate exceeded signal indicating that memory traffic flow from a traffic source (302) exceeds a threshold; receive a distress signal from a memory controller (304) that interfaces with a memory device (306A, 306B), the distress signal indicating that the memory device (306A, 306B) is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source (302) when the rate exceeded signal and the distress signal are both asserted.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete