Phasenvoreinstellung für Schnellen Chirp-Phasenregelkreis

Details

Veröffentlichungs-Nr.

EP3579012

Aktenzeichen

EP18305690

Anmeldetag

6. Juni 2018

Veröffentlichung

30. März 2022

Erteilung

30. März 2022

Rechtsraum

EP

IPC

G01S7/03G01S7/35G01S7/40G01S13/34G01S13/93H03L7/093H03B1/04H03C3/09H03L7/089H03L7/18H03L7/22// G01S13/28

Abstract

A fast chirp Phase Locked Loop (70) with a phase preset includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit (86) connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current (98) during a start frequency time (302) preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA

Fachgebiete