Prefetcher für Verspätete Unregelmässige Lasten

Details

Veröffentlichungs-Nr.

EP3588311

Aktenzeichen

EP19175813

Anmeldetag

21. Mai 2019

Veröffentlichung

1. September 2021

Erteilung

1. September 2021

Rechtsraum

EP

IPC

G06F12/0862

Abstract

Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA

Fachgebiete