Prozessoranweisungsunterstützung zur Abwehr von Seitenkanalangriffen

Details

Veröffentlichungs-Nr.

EP3588314

Aktenzeichen

EP19177146

Anmeldetag

28. Mai 2019

Veröffentlichung

19. April 2023

Erteilung

19. April 2023

Rechtsraum

EP

IPC

G06F12/14

Abstract

<div notation="docdba" type="abstract" xml:lang="en"><p>Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.</p></div>

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete