Beschleunigersysteme und Verfahren für Matrixoperationen

Details

Veröffentlichungs-Nr.

EP3716051

Aktenzeichen

EP20156846

Anmeldetag

12. Februar 2020

Veröffentlichung

3. September 2025

Erteilung

3. September 2025

Rechtsraum

EP

IPC

G06F9/30G06F9/38

Abstract

The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry. Communication between the RS circuitry 134 and the TMU provides the RS circuitry with notification of successfully executed operations and allows the RS circuitry to cancel operations where the operations are associated with branch mispredictions and/or non-retired speculatively executed instructions.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete