Stromspiegelanordnungen mit Reduzierter Eingangsimpedanz

Details

Veröffentlichungs-Nr.

EP3859486

Aktenzeichen

EP21151893

Anmeldetag

15. Januar 2021

Veröffentlichung

13. Dezember 2023

Erteilung

13. Dezember 2023

Rechtsraum

EP

IPC

G05F3/26H03F1/34H03F3/34H03F1/30

Abstract

An example current mirror arrangement (300) includes a current mirror circuit having an input transistor (Q1) and an output transistor (Q2), where the base/gate terminal of the input transistor is coupled to its collector/drain terminal via a transistor matrix that includes a plurality of transistors (Q3,Q4,Q5,Q6). Transistors of the transistor matrix, together with the input transistor, form two parallel feedback loops (390-1,390-2), such that the input transistor is part of both loops. The first loop (390-1) is a fast, low-gain loop, while the second loop (390-2) is a slow, high-gain loop. At lower input frequencies, the high-gain loop may properly bias and accurately generate voltage at the base/gate terminal of the input transistor, while at higher input frequencies the fast loop may significantly extend the linear operating frequency band. Consequently, a current mirror arrangement with improvements in terms of linearity and signal bandwidth may be realized.

Anmelder

Firma

Analog Devices, Inc.

Land

🇺🇸 USA

Fachgebiete