Hardware-Beschleunigervorrichtung, Zugehöriges System und Verfahren zum Betrieb

Details

Veröffentlichungs-Nr.

EP4009174

Aktenzeichen

EP21209056

Anmeldetag

18. November 2021

Veröffentlichung

26. Februar 2025

Erteilung

26. Februar 2025

Rechtsraum

EP

IPC

G06F11/16

Abstract

A hardware accelerator device comprises a set of processing circuits (160) arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network (162). The processing circuits (160) are configurable to read (200) first input data from said data memory banks via the interconnect network (162) and the memory controller, process (20) said first input data to produce output data, and write (204) said output data into said data memory banks via the interconnect network (162) and the memory controller. The hardware accelerator device comprises a set of configurable lockstep control units (169) which interface the processing circuits (160) to the interconnect network (162). Each configurable lockstep control unit (169) is coupled to a subset of processing circuits (160) and is selectively activatable to operate in a first operation mode, or in a second operation mode. In the first operation mode, the lockstep control unit (169) is configured to compare data read requests and/or data write requests issued towards said memory controller by a first (160<0>) and a second (160<1>) processing circuits in the subset of processing circuits to detect a fault. In the second operation mode, the lockstep control unit (169) is configured to propagate towards said memory controller said data read requests and/or data write requests issued by the first (160<0>) and by the second (160<1>) processing circuits in the subset of processing circuits (160).

Anmelder

Firma

STMicroelectronics S.r.l.

Land

🇮🇹 Italien

Fachgebiete