Ferrero, Alberto

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

A system (200) to monitor a MOSFET (102), the system including a switching arrangement (202) configured to switchably isolate a gate terminal (102G) of the MOSFET (102) and a source terminal (102S) of the MOSFET (102) from a gate-control voltage source ((104) and a test circuit (204) configured to detect a change in a gate-to-source voltage of the MOSFET (102) over a test period, the test period occurring while the gate terminal (102G) and the source terminal (102S) are isolated.

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In a DC-DC converter (200'), a layout is designed to enable utilization of the conductive trace connecting the converter output node (N2) to an output bump (BB1, BB2) at which the load (RL, CL) is attached as a sense resistor (Rs). The layout forces the output current down into lower metallization levels (201) of an interconnect layer reaching the converter output node (N2) before the output current flows up into this conductive trace (212) and out through the output bump (BB1, BB2). The conductive trace (212) includes resistive pillars connected in parallel or series between the lower metallization levels (201) and a top metallization layer (207c) of the conductive trace (212), with these resistive pillars being substantially greater in resistance than the lower metallization levels (201) and the top metallization layer (207c) of the conductive trace (212).

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A hardware accelerator device comprises a set of processing circuits (160) arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network (162). The processing circuits (160) are configurable to read (200) first input data from said data memory banks via the interconnect network (162) and the memory controller, process (20) said first input data to produce output data, and write (204) said output data into said data memory banks via the interconnect network (162) and the memory controller. The hardware accelerator device comprises a set of configurable lockstep control units (169) which interface the processing circuits (160) to the interconnect network (162). Each configurable lockstep control unit (169) is coupled to a subset of processing circuits (160) and is selectively activatable to operate in a first operation mode, or in a second operation mode. In the first operation mode, the lockstep control unit (169) is configured to compare data read requests and/or data write requests issued towards said memory controller by a first (160<0>) and a second (160<1>) processing circuits in the subset of processing circuits to detect a fault. In the second operation mode, the lockstep control unit (169) is configured to propagate towards said memory controller said data read requests and/or data write requests issued by the first (160<0>) and by the second (160<1>) processing circuits in the subset of processing circuits (160).