Verfahren zur Herstellung eines Gate-Schnitts in einem Halbleiterbauelement

Details

Veröffentlichungs-Nr.

EP4033522

Aktenzeichen

EP21153044

Anmeldetag

22. Januar 2021

Veröffentlichung

18. Juni 2025

Erteilung

18. Juni 2025

Rechtsraum

EP

IPC

H10D84/01H10D84/83H01L21/768H01L21/74H01L23/528H01L23/535H10D84/03

Abstract

According to the invention, an array of nano-sized semiconductor fins (1) is processed on a semiconductor substrate (2), wherein rails (5) are buried in the substrate and in a layer of dielectric material that is isolating neighbouring fins from each other. The rails (5) extend in the direction of the fins and each rail is situated between two adjacent fins (1). The rails may be buried power rails as known in the art for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures (14,15,16) are produced by methods known as such in the art, preferably using a replacement gate technique. The gate structures extend transversally, preferably perpendicularly, with respect to the fins (1) and the rails (5). According to the invention, a gate cut is produced by forming an opening (22) from the back side of the substrate, and removing a portion of the gate structure at the bottom of said opening, thereby creating a gate cut that is aligned to the sidewalls of the rail (5). The invention is equally related to a semiconductor component, such as an integrated circuit, characterized by the fact that it comprises a gate cut that is aligned to the sidewalls of a buried contact rail (5,25).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete