Systeme und Verfahren zur Symbolabstandsabhängigen Musteranpassenden Doppelschleifen-Taktrückgewinnung für Serielle Hochgeschwindigkeitsverbindungen

Details

Veröffentlichungs-Nr.

EP4060929

Aktenzeichen

EP22162967

Anmeldetag

18. März 2022

Veröffentlichung

8. November 2023

Erteilung

8. November 2023

Rechtsraum

EP

IPC

H04L7/00H03L7/091H04L25/03

Abstract

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Anmelder

Firma

Samsung Display Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete