Adaptive Wortleitungsuntersteuerung für einen Speicherinternen Rechenvorgang mit Gleichzeitigem Zugriff auf Mehrere Zeilen eines Statischen Direktzugriffsspeichers (sram)

Details

Veröffentlichungs-Nr.

EP4116975

Aktenzeichen

EP22182469

Anmeldetag

1. Juli 2022

Veröffentlichung

28. August 2024

Erteilung

28. August 2024

Rechtsraum

EP

IPC

G11C7/04G11C8/08G11C11/412G11C11/418G11C7/10

Abstract

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete