Selektive Bitleitungsklemmsteuerung für Speicherinterne Rechenoperation mit Gleichzeitigem Zugriff auf Mehrere Zeilen eines Statischen Direktzugriffspeichers

Details

Veröffentlichungs-Nr.

EP4116976

Aktenzeichen

EP22183496

Anmeldetag

7. Juli 2022

Veröffentlichung

28. August 2024

Erteilung

28. August 2024

Rechtsraum

EP

IPC

G11C7/04G11C7/10G11C7/12G11C11/419G11C7/06

Abstract

A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete