Verfahren zur Herstellung einer Eingelassenen Verbindungsschiene eines Integrierten Schaltungschips

Details

Veröffentlichungs-Nr.

EP4135016

Aktenzeichen

EP21190833

Anmeldetag

11. August 2021

Veröffentlichung

25. Februar 2026

Erteilung

25. Februar 2026

Rechtsraum

EP

IPC

H01L21/768H01L23/48H01L23/528H01L23/535

Abstract

According to the method of the invention, a trench (10) is formed in a semiconductor layer (1) of a device wafer for the fabrication of ICs, followed by the deposition of a liner (11) on the sidewalls of the trench. The liner is removed from the bottom of the trench, and the trench may be deepened anisotropically to form an extension (12) of the trench. This may be done along the full length of the trench, or locally by applying a mask. An etch process is then applied wherein the semiconductor material is removed outwardly from the extension, thereby creating a cavity (13) that is wider than the trench. The etch process is selective relative to the liner (11), so that the cavity is formed essentially below the liner (11). Then the combined space formed by the trench and the cavity is filled with an electrically conductive material, possibly after forming a second liner (14). This results in the formation of a buried interconnect rail (15) comprising a narrow portion (15a) in the area of the trench and a wider portion (15b) in the area of the cavity. The wider portion may be contacted from the back side of the semiconductor layer by a TSV connection (24), enabling a large contact area between said TSV connection and the buried rail. The selectivity of the etch process applied for forming the cavity (13) results in the formation of the cavity (13) and thereby of the wider rail portion (15b) at a location that is remote from the active devices formed on the front surface of the semiconductor layer (1).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete