Halbleiterbauelement mit Rückseiten-I/o-Signalführung

Details

Veröffentlichungs-Nr.

EP4187600

Aktenzeichen

EP21210849

Anmeldetag

26. November 2021

Veröffentlichung

3. September 2025

Erteilung

3. September 2025

Rechtsraum

EP

IPC

H01L21/768H01L23/522H01L23/528H01L23/48H01L23/535H10D89/60

Abstract

The invention is related to a semiconductor component, for example an integrated circuit chip, comprising a semiconductor substrate (1) having active devices (7) at the front side thereof and I/O terminals (19) at the back side of the component. The terminals are connected to the active devices through TSV connections (16b) and buried rails (15b) in an area (5) of the substrate that is separate from the area (4) in which the active devices are located. According to the invention, the I/O TSV connections (16b) are located in a floating well (25) of the substrate that is separated from the rest of the substrate by a second well (26) formed of material of the opposite conductivity type compared to the material of the floating well. The second well (26) comprises at least one contact (28) configured to be coupled to a voltage that is suitable for reverse-biasing the junction (27) between the floating well (25) and the second well (26). In this way, a small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. According to preferred embodiments, additional contacts and conductors are provided which are configured to create an ESD protection circuit for protecting the I/O TSVs (16b) and the I/O rails (15b) from electrostatic discharges.

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete