Vertikales Metallmessverfahren für einen Gleichstromwandler

Details

Veröffentlichungs-Nr.

EP4235195

Aktenzeichen

EP23157895

Anmeldetag

22. Februar 2023

Veröffentlichung

18. Juni 2025

Erteilung

18. Juni 2025

Rechtsraum

EP

IPC

G01R1/20H02M1/00G01R19/00G01R19/32H02M3/07

Abstract

In a DC-DC converter (200'), a layout is designed to enable utilization of the conductive trace connecting the converter output node (N2) to an output bump (BB1, BB2) at which the load (RL, CL) is attached as a sense resistor (Rs). The layout forces the output current down into lower metallization levels (201) of an interconnect layer reaching the converter output node (N2) before the output current flows up into this conductive trace (212) and out through the output bump (BB1, BB2). The conductive trace (212) includes resistive pillars connected in parallel or series between the lower metallization levels (201) and a top metallization layer (207c) of the conductive trace (212), with these resistive pillars being substantially greater in resistance than the lower metallization levels (201) and the top metallization layer (207c) of the conductive trace (212).

Anmelder

Firma

STMicroelectronics Asia Pacific Pte Ltd.

Land

🇸🇬 Singapur

Fachgebiete