Halbleitervorrichtungssystem

Details

Veröffentlichungs-Nr.

EP4318254

Aktenzeichen

EP22189135

Anmeldetag

5. August 2022

Veröffentlichung

24. September 2025

Erteilung

24. September 2025

Rechtsraum

EP

IPC

G06F15/78

Abstract

There is disclosed a semiconductor device system comprising a central controller (1) and a plurality of hardware nodes (2, 3, 4) implemented in application-specific integrated circuit, ASIC, the hardware nodes (2, 3, 4) being mutually interconnected with each other through a plurality of hard-wired connections (2.4, 3.4, 4.4) which support the transmissions of globally asynchronous continuous-time binary value, CTBV, signals, in such a way that each hard-wired connection supports the propagation of one unique CTBV signal from first transmitting hardware node connected to the hard-wired connection to at least one receiving hardware node connected to the hard-wired connection, so as to define at least one point-to-point(s) communication path between at least two hardware nodes, configured as processing nodes (2, 3), along a sequence of hard-wired connections connected to each other through at least one switching circuitry (12'). The at least one switching circuitry (12') is controlled by at least one hardware node, of the plurality of hardware nodes, which is configured as communication node, the at least one switching circuitry (12') being configured to selectably connect, based on configuration data, at least two hard-wired connections in the sequence of hard-wired connections, so as to permit the transmission of each CTBV signal along the sequence of hard-wired connections, wherein the at least one switching circuitry (12') is latency-deterministic. Each hardware node of the plurality of hardware nodes is configured to download configuration data through a package-switched configuration communication path (9).

Anmelder

Firma

Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Land

🇩🇪 Deutschland

Fachgebiete