Mimcap-Anordnung und Verfahren zu dessen Herstellung

Details

Veröffentlichungs-Nr.

EP4391047

Aktenzeichen

EP22214723

Anmeldetag

19. Dezember 2022

Veröffentlichung

8. Oktober 2025

Erteilung

8. Oktober 2025

Rechtsraum

EP

IPC

H01L23/522H10D1/68// H01L21/768

Abstract

The invention is related to semiconductor components such as integrated circuit chips, comprising a multilayer structure such as a back end of line portion, with a plurality of MIM capacitors integrated between two levels of the multilayer structure. The capacitors are realized as an assembly of capacitors, in the form of a stack of at least three electrically conductive layers (20,21,22;50-53) , separated by dielectric layers (23,24,54-56), and formed conformally on a topography defined by a plurality of dielectric pillars (13) distributed on a bottom conductive plate (10) formed on a first level (Mn) of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate conductive layers of the stack become available for contacting said layers by via connections (5,8,35,60-63,70-72) of the next level of the interconnect structure. In this way, a circuit comprising multiple parallel capacitors can be realized, which significantly increases the capacitance of the overall assembly. The method of the invention includes the deposition of a thick dielectric layer (11a) and one or more additional dielectric layers (11a,11b, 11c, 11d) thereon. Openings (30,40,41) are produced in the additional layers before patterning the layers to form the pillars, so that the thicknesses of the additional layers determine the height differences between the pillars. By carefully controlling said thicknesses in relation to the thicknesses of the layers of the capacitor assembly, contacting of the intermediate conductive layers of the stack is enabled.

Anmelder

Firmen

IMEC VZW
Imec VZW

Land

🇧🇪 Belgien

Fachgebiete