Symmetrischer Statischer Direktzugriffspeicher (sram)

Details

Veröffentlichungs-Nr.

EP4621783

Aktenzeichen

EP25151737

Anmeldetag

14. Januar 2025

Veröffentlichung

24. September 2025

Rechtsraum

EP

IPC

G11C11/412G11C11/419H10B10/00

Abstract

Embodiments herein relate to a balanced eight-transistor (8T) static random-access memory (SRAM) cell having four n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) and four p-type MOSFETS. An nMOS write port and two pMOS read ports are optimized with a complementary field-effect transistor (CFET) process to achieve a high density. The cell is reconfigurable for various port configurations including 1R1W (1-read 1-write), 2R1W (2-read 1-write), 3R1W (3-read 1-write), 4R1W (4-read 1-write) and single/dual-ported SRAM with appropriate Vt (voltage threshold) targeting.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete