Hochdichte Gestapelte Transistoren mit Unabhängigen Gates

Details

Veröffentlichungs-Nr.

EP4651673

Aktenzeichen

EP25168904

Anmeldetag

7. April 2025

Veröffentlichung

19. November 2025

Rechtsraum

EP

IPC

H10D84/01H10D30/01H10D30/00H10D84/03H10D88/00

Abstract

A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent gates around subsets of nanoribbons in the stack. In previous nanoribbon transistors, a gate electrode wraps around all of the semiconductor regions and spans the areas between adjacent semiconductor regions, thus electrically coupling the centers of the semiconductor regions. To achieve a stack of semiconductor regions with independent gates, adjacent nanoribbons in the stack may be set at different distances apart, or two or more sacrificial materials may be included when forming the stack of semiconductor materials and selectively etched when forming different gates.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA

Fachgebiete