Verfahren zur Herstellung einer Halbleiter-Bauelement-Anordnung

Details

Veröffentlichungs-Nr.

EP4668319

Aktenzeichen

EP24183356

Anmeldetag

20. Juni 2024

Veröffentlichung

24. Dezember 2025

Rechtsraum

EP

IPC

H01L21/48H01L23/14H01L23/538H01L23/00H01L25/065H01L25/00

Abstract

The method of the invention is related to the assembly of two components on two opposite sides of a substrate (1), enabled by the embedding of one of the components in a stress-compensated SiO<2> layer (14) applied at low temperatures, i.e. lower than any temperature that could compromise the functionality of the embedded component. Preferred embodiments are related to heterogeneous integration schemes, i.e. the assembly of components of different types, such as a CMOS chip (12) and a III-V chip (22), which are otherwise difficult to integrate in a 3D package. The stress-compensated film (14) embeds the component at least laterally, i.e. the layer surrounds and is in direct contact with the sides of the component and the thickness of the film is at least equal to the thickness of the component.

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete